Description
Technical Specifications:
- Architecture: CMOS PLD
- Logic Gates: Programmable logic array with 8 macrocells
- Propagation Delay: 15ns
- Package Type: 20-pin PDIP
- Operating Voltage: 5V
- Power Dissipation: Low power consumption
- Programming Endurance: Supports multiple reprogramming cycles
- Operating Temperature Range: 0°C to 70°C
- Compliance: RoHS compliant
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